Simulink® Design Verifier™

Verification Subsystem - Represent subsystem that specifies proof or test objectives without impacting simulation results or generated code

Library

Simulink Design Verifier

Description

This block is a Subsystem block that is preconfigured to serve as a starting point for creating a subsystem that specifies proof or test objectives for use with the Simulink Design Verifier software. The Real-Time Workshop software ignores Verification Subsystem blocks during code generation, behaving as if the subsystems do not exist. A Verification Subsystem block allows you to add Simulink Design Verifier components to a model without affecting its generated code.

To create a Verification Subsystem in your model:

1. Copy the Verification Subsystem block from the Simulink Design Verifier library into your model.

2. Open the Verification Subsystem block by double-clicking it.

3. In the Verification Subsystem window, add blocks that specify proof or test objectives. Use Inport blocks to represent input from outside the subsystem.

The Verification Subsystem block in the Simulink Design Verifier library is preconfigured to work correctly. For correct behavior, a Verification Subsystem block must

• Contain no Outport blocks.

• Enable its Treat as Atomic Unit parameter.

• Specify its Mask type parameter as VerificationSubsystem.

Note   If you alter a Verification Subsystem block so that it no longer behaves correctly, the Simulink Design Verifier software displays a warning.

See the Subsystem block in the Simulink Reference and Creating Subsystems in Simulink User's Guide for more information.

Examples

The sldvdemo_debounce_validprop demo model includes a Verification Subsystem that specifies two proof objectives, as shown in the following figure.

See Also

Proof Assumption, Proof Objective, Test Condition, Test Objective

Test Objective

Configuration Parameters