| Embedded IDE Link™ VS | |
Target Preferences in Embedded IDE Link VS
Options on the block mask let you set features of code generation for your custom Blackfin, SHARC, or TigerSHARCprocessor. Adding this block to your Simulink software model provides access to the processor hardware settings you need to configure when you generate code from Real-Time Workshop software to run on the processor.
Any model that you target to custom hardware must include this block. Real-Time Workshop software returns an error message if a target preferences block is not present in your model.
Note This block must be in your model at the top level and not in a subsystem. It does not connect to other blocks, but stands alone to set the target preferences for the model. Simulink software returns an error when your model either does not include a target preferences block or has more than one. |
You can specify the following processor and target options on this block:
Board and processor information
Memory mapping and layout
Allocation of the various code sections, such as compiler, and custom sections
Setting the options included in this dialog box results in identifying your target to Real-Time Workshop, VisualDSP++, and Simulink software, and configuring the memory map for your target. Both steps are essential for developing code for any processor that is custom or explicitly supported.
Unlike most other blocks, you cannot open the block dialog box for this block until you add the block to a model. When you try to open the block dialog, the block attempts to connect to a VisualDSP++ IDE session. It cannot make the connection when the block is in the library. If you try to open the block dialog before you add it to a model, the open process fails and returns an error message.
Note If you do not have VisualDSP++ software installed on your PC, you cannot open this block dialog. |
Real-Time Workshop software provides the capability to generate code from a selected subsystem in a model. To generate code for an Analog Devices processor from a subsystem, the subsystem model must include this target preferences block.
This section contains the following subsections:
All target preferences block dialog boxes provide tabbed access to the following panes. You set the options for the processor from these panes:
Board info — Select the board type and processor, set the clock speed, and identify the session.
Memory — Set the memory allocation and layout on the processor (memory mapping).
Sections — Determine the arrangement and location of the sections on the processor, such as where to put the compiler information.
The following options appear on the Board Info pane for the Target Preferences dialog box.
Enter the type of board you are targeting with the model. You can enter Custom to support any board, based on one of the supported processors, or enter the name of one of the supported boards.
Select the processor on the board you select in Board type. The processor type you enter determines the contents and setting for options on the Memory and Sections panes in this dialog box.
Shows the clock speed of the processor. When you enter a value, you are not changing the CPU clock rate. Instead, you are reporting the actual rate. If the value you enter does not match the rate on the processor, your model's real-time code profiling results may be incorrect.
Enter the actual clock rate the board uses. The rate you enter in this field does not change the rate on the board. Setting CPU clock to the actual board rate allows the code you generate to run correctly according to the actual clock rate of the hardware.
When you generate code for targets from Simulink software models, you may encounter the software timer. The timer is invoked automatically to handle and create interrupts to drive your model if the processing rates in your model change (the model is multirate).
Correctly generating interrupts for your model depends on the clock rate of the CPU on your processor.
For the timer software to calculate the interrupts correctly, VisualDSP++ software needs to know the actual clock rate of your processor as you configured it. CPU clock speed lets you tell the timer the rate at which your processor CPU runs, which is the rate to use to match the CPU rate.
The timer uses the CPU clock rate you specify in CPU clock to calculate the time for each interrupt. For example, if your model includes a sine wave generator block running at 1 kHz feeding a signal into an FIR filter block, the timer needs to create interrupts to generate the sine wave samples at the proper rate. The timer uses the clock rate you enter, for example, 100 MHz, to calculate the sine generator interrupt period as follows for the sine block:
Sine block rate = 1 kHz, or 0.001 s/sample
CPU clock rate = 100 MHz, or 0.000000001 s/sample
To create sine block interrupts at 0.001 s/sample requires:
100,000,000/1000 = 1 Sine block interrupt per 100,000 clock ticks
Thus, you must report the correct clock rate, or the interrupts come at the wrong times and the results are incorrect.
Entries in this group let you specify the locations of custom source files or libraries or other functions. The following options provide access to text areas where you enter files and file paths. The block does not check whether the functions you enter are correct or the file paths you provide exist and are correct. Entering incorrect functions or paths may cause errors during code generation.
Source files — Enter the full paths to source code files to use with this processor. By default, there are no entries in this parameter.
Include paths — If you require additional files on your path, add them by typing the path into the text area. The default setting does not include additional paths.
Libraries — These entries identify specific libraries that the processor requires. They appear on the list by default if required. Add more as you require by entering the full path to the library with the library file in the text area. No additional libraries appear in this field in the default configuration.
Initialize functions — If your project requires an initialize function, enter it in this field. By default, this parameter is empty.
Terminate functions — Enter a function to run when a program terminates. The default setting is not to include a specific termination function.
When you enter a path to a file, library, or other custom code, use the string
$(install_dir)
to refer to the VisualDSP++ software installation directory.
Enter new paths or files (custom code items) one entry per line. Include the full path to the file for libraries and source code. Board custom code options do not support functions that use return arguments or values. Only functions of type void fname void are valid as entries in these parameters.
Contains a list of all the sessions defined in VisualDSP++ IDE. From the list of available sessions, select the one to which you are targeting your code.
Lists the processors on the board you selected for targeting in Session name. In most cases, only one name appears because the board has one processor. In the multiprocessor case, you select the processor by name from the list.
When you develop models for any processor, you need to specify the layout of the physical memory on your processor and board to determine how use it for your program. For supported boards, the board-specific target preferences blocks set the default memory map.
The Memory pane contains memory options in three areas:
Physical Memory — Specify the processor and board memory map
Heap — Specify whether you use a heap and determine the size in words
Cache configuration — Enables the cache (where available) and sets the size in kilobytes
Note Your Physical Memory, Heap, and Cache configuration settings on this pane may affect options on the Sections pane. Your choices on the Memory pane may change how you configure some options on the Sections pane. |
Most of the information about memory segments and memory allocation is available from the online help system for the VisualDSP++ product.
This list shows the physical memory segments available on the board and processor. By default, target preferences blocks show the memory segments found on the selected processor. In addition, the Memory pane on preconfigured target preferences blocks shows memory segments that are available on the board, but that are external to the processor (external memory). Target preferences blocks set default starting addresses, lengths, and contents of the default memory segments.
The default memory segments for each processor and board are different. For example:
Custom boards based on Blackfin processors provide SRAM memory segments by default.
SHARC-based boards provide RAM memory segments by default.
When you highlight an entry on the Physical memory list, the name of the entry appears in this field. To change the name of the existing memory segment, select it in the Physical memory list and then type the new name in this field.
Note You cannot change the names of default processor memory segments. |
To add a new physical memory segment to the list, click Add, replace the temporary label in Name with the one to use, and press Return. Your new segment appears on the list.
After you add the segment, you can configure the starting address, length, and contents for the new segment. New segments start with code and data as the type of content that can be stored in the segment (refer to the Contents option).
Names are case sensitive. NewSegment is not the same as newsegment or newSegment.
Address reports the starting address for the memory segment showing in the Name field. Address entries are in hexadecimal format and limited only by the board or processor memory.
When you are using a processor-specific preferences block, the starting address shown is the default value. You can change the starting value by entering the new value directly in the Address field when you select the memory segment to change.
From the starting address, Length sets the length of the memory allocated to the segment in the Name field. As in all memory entries, specify the length in hexadecimal format, in minimum addressable data units (MADUs).
When you are using a processor-specific preferences block, the length shown is the default value. You can change the value by entering the new value directly in this option.
Contents details the kind of program sections that you can store in the memory segment in Name. As the processor type for the target preferences block changes, the kinds of information you store in listed memory segments may change. Generally, the Contents list contains these strings:
Code — Allow code to be stored in the memory segment in Name.
Data — Allow data to be stored in the memory segment in Name.
Code and Data — Allow code and data to be stored in the memory segment in the Name field. When you add a new memory segment, this string is the default setting for the contents of the new element.
You may add or use as many segments of each type as you need, within the limits of the memory on your processor.
Click Add to add a new memory segment to the processor memory map. When you click Add, a new segment name appears, for example NEWMEM1, in Name and on the Physical memory list. In Name, change the temporary name NEWMEM1 by entering the new segment name. Entering the new name or clicking Apply updates the temporary name on the list to the name you enter in this field.
Remove a memory segment from the memory map. Select the segment to remove on the Physical memory list, and click Remove to delete the segment.
Displays all available memory banks for the selected processor. When you select one of the entries on this list, the Name, Address, Length, and Contents parameters change to reflect the memory block selection. With the contents list, you can change the type of material stored in the block—data or code or both.
If your processor supports using a heap, as the Blackfin and SHARC processors do, selecting this option enables creating the heap, and enables the Heap size option. Create heap is not available on processors that either do not provide a heap or do not allow you to configure the heap.
Use this option to create a heap in any memory segment on the Physical memory list. Select the memory segment on the list, and then select Create heap to create a heap in the selected segment. After you create the heap, use the Heap size and Define label options to configure the heap.
The location of the heap in the memory segment is not under your control. The only way to control the location of the heap in a segment is to make the segment and the heap the same size. Otherwise, the compiler determines the location of the heap in the segment.
After you select Create heap, this option lets you specify the size of the heap in words. Enter the number of words in decimal format. When you enter the heap size in decimal words, the system converts the decimal value to hexadecimal format. You can enter the value directly in hexadecimal format as well. Processors may support different maximum heap sizes.
Selecting Create heap enables this option that allows you to name the heap. Enter your label for the heap in the Heap label option.
Use this option which you enable by selecting Define label, to provide the label for the heap. Any combination of characters is accepted for the label, except reserved characters in ANSI C/C++ compilers.
The block does not verify that the label you enter is valid. Invalid labels can cause errors during code generation.
Blackfin, SHARC, and TigerSHARC processors support different cache arrangements. For Blackfin processors, you can select one of the following options from the list:
L1_Code_CACHE
L1_DataA_CACHE
L1_DataB_CACHE
On SHARC processors, the cache is always Instruction_CACHE. Set the cache size in Configuration.
On TigerSHARC processors, the cache is always CACHE, used for both data and code, and you can only enable the cache. You cannot choose the size or configuration. Use the Configuration option to enable the cache.
Select the size of the cache from the list to determine the size of the cache allocated. SHARC processors support 1536 bits or 0 bits (no cache). Blackfin processors support 0 bits or 16 bits. For TigerSHARC processors, your choices are disable or enable only.
Options on this pane let you specify where various program sections should go in memory. Program sections are distinct from memory segments—sections are portions of the executable code stored in contiguous memory locations. Commonly used sections include .program, .bsz, .data1, and .stack.
For more information about program sections and objects, refer to the Analog Devices VisualDSP++ product online help.
Within this pane, you allocate the memory needed for the Default sections and Custom sections.
The following table provides brief definitions of the sections in the Default sections, and Custom sections lists in the pane. All sections do not appear for all processors.
String | Description of the Section Contents |
|---|---|
bsz | Global zero initialized data |
bsz_init | Run-time initialization data |
constdata | Constant data, usually defined with the ANSI C qualifier and string constants |
cplb_code | CPLB management routines |
cplb_data | CPLB configuration tables |
data1 | Global program data for execution |
heap | System heap allocation |
L1_Data_A | L1 band A SRAM data |
L1_Data_B | L1 band B SRAM data |
| noncache_code | Code not assigned to the cache |
| program | Program code |
| seg_argv | Command line arguments that PGO uses |
| seg_dmda | Global data |
| seg_heap | System heap |
| seg_init | Stack and heap location and size info |
| seg_int_code | Interrupt latch register modifier code |
| seg_pmco | Program code |
| seg_pmda | Global program data qualified with pm keyword |
| seg_rth | Interrupt vector table |
| seg_stak | System stack |
stack | Global system stack |
| voldata | Volatile data |
You can learn more about memory sections and objects in your Analog Devices VisualDSP++ product online help.
During program compilation, the compiler produces both uninitialized and initialized blocks of data and code. These blocks get allocated into memory as required by the configuration of your system. On the Default sections list you find both initialized sections that contain data or executable code and uninitialized sections that reserve space in memory.
The following sections are initialized:
bsz
bsz_init
constdata
seg_pmco
seg_pmda
voldata (created by the assembler)
The following sections are not initialized:
(created by the assembler)
heap
stack
The following sections appear on the list as well:
(created by the assembler)
Note The ANSI C/C++ compiler does not use the .data section. |
When you highlight a section on the list, Section description shows a brief description of the section. Also, Placement shows you where the section is presently allocated in memory.
Describes the contents of the selected entry on the Default sections list.
Shows you where the selected Default sections list entry is allocated in memory. You change the memory allocation by selecting a different location from the Placement list. The list contains the memory segments as defined in the physical memory map on the Memory pane. Select one of the listed memory segments to allocate the highlighted compiler section to the segment.
When your program uses code or data sections that are not included in the Default sections list, add the new sections to this list. Initially, the Custom sections list parameter contains no fixed entries. Only a placeholder for a section for you to define.
Enter the name for your new section in this field. To add a new section, click Add. Then, replace the temporary name with the name to use. Although the temporary name includes a period at the beginning you do not need to include a period in your new name. Names are case sensitive. NewSection is not the same as newsection, or newSection.
Select the kind of data to assign to the new section. Choose from one of the following list entries:
Any — Indicates the section can store either code or data. New sections use Any by default.
Code — Indicates the section stores code.
Data — Indicates the section stores data.
Not used.
After you have added the new section to the Name list, select the memory segment to which to add your new section. Limited only by the restrictions imposed by the hardware and compiler, you can select any segment that appears on the list.
Click Add to add a new entry on the list of custom sections. When you click Add, a new temporary name, for example NEWMEM1 appears in the Name field. Enter the new custom section name to add the section to the Custom sections list. After you enter the new name, click Apply to add the new section to the list. You can also click OK to add the section to the list and close the dialog box.
Remove a section from the Custom sections list. To remove a section, select the section, and click Remove.
Clicking Add new on the General paneopens this dialog box to add a new processor to the list of supported processors. The new processor must be a member of one of the supported families of processors.
The first time you click Save to add a new processor definition to the list of supported processors, a dialog box opens that directs you to select a destination folder for the saved processor definitions file customChipInfo.dat. You must select a directory to which you have write access. The location you specify becomes part of your MATLAB software preferences. Future processors that you add become entries in the file customChipInfo.dat.
To add a new processor, enter values for the following parameters:
Provide a name to identify your new processor. You can use any valid ANSI C string value in this field. The name you enter in this field appears on the list of processors after you add the new processor.
Identifies the class of the new processor. Your new processor must be a member of a family of processors that Embedded IDE Link VS software supports. For example, you can add a new Blackfin processor because the product supports the Blackfin processor family.
Provide a name to identify your new processor. You can use any valid ANSI C string value in this field. The name you enter in this field appears on the list of processors after you add the new processor.
Enter the clock speed of the processor in MHz. When you enter a value, you are not setting the CPU clock rate on the processor. You are reporting the rate. If the value you enter does not match the rate on the processor, your model's real-time results may be wrong, and code profiling results are not correct.
Setting CPU clock to the actual board rate allows the generated code to run correctly according to the actual clock rate of the hardware.
This string ensures that the compile operation works successfully.
This string provides the prefix that the calling code uses to call hook functions during code generation.
Parameters in this group configure the memory map for the new processor.
Parameters in this group configure the default sections for your new processor.
If you do not provide an entry for each of these parameters, Embedded IDE Link VS software returns an error message and does not create the new processor entry.
Provide a name to identify your new processor. You can use any valid ANSI C string in this field. The name you enter appears on the list of processors after you add the new processor.
Enter the clock speed of the processor in MHz. When you enter a value, you are not setting the CPU clock rate on the processor. You are reporting the rate. If the value you enter does not match the rate on the processor, your model's real-time results and code profiling results may not be correct.
Setting CPU clock to the actual board rate allows the code you generate to run correctly according to the actual clock rate of the hardware.
This represents the class for the new processor. New processors must be members of processor families that Embedded IDE Link VS software supports, such as a new Blackfin or TigerSHARC processor.
You cannot add a new processor class to support your new processor.
Generally, processors in a family share common design elements such as interrupt architecture and clock. They may have different memory maps. By selecting the processor class, you identify the common features of the processor family. The parameters in Define internal memory banks and Define default sections enable you to specify the memory mapping for your new processor.
For example, to add a new Blackfin processor, enter the string BFxxx where xxx is the processor number.
The following table shows the strings for the supported processor families.
| Processor Family | Processor Class String |
|---|---|
| Blackfin | BFxxx where xxx is the numerical designation of the processor, such as BF532 |
| SHARC | xxxxx where xxxxx is the numerical designation for the processor, such as 21366 |
| TigerSHARC | xxx where xxx is the numerical designation for the processor, such as 202 |
Here is an example of using the code generation hook when you begin to generate a project from a model intended for the BF532 processor. At the start of the code generation process, the process calls BFxxx_validateModelEntry.m to validate the model settings for the processor. The BFxxx prefix is the code generation hook.
Identifies the processor family of the new processor to the compiler. Successful compilation requires this switch. The string depends on the processor family or class. The software does not use this string.
This string represents a prefix to add when the code generation process call certain hook functions. The hook allows the code to call into handling functions that are specific to the processor selected.
The code generation hook strings for the supported processors appear in the following table.
| Processor Class or Family | Code Generation Hook String |
|---|---|
| Blackfin | blackfin |
| SHARC | sharc |
| TigerSHARC | tigersharc |
To add a new physical memory segment to the internal memory banks list, click Add, replace the temporary label in Name with the one to use, and press Return. Your new segment appears on the list.
After you add the segment, you can configure the starting address, length, and contents for the new segment. New segments start with code and data as the type of content that can be stored in the segment (refer to the Contents option).
Names are case sensitive. NewSegment is not the same as newsegment or newSegment.
Address reports the starting address in hexadecimal format for the memory segment showing in Name. Address entries are limited only by the board or processor memory.
When you are using a processor-specific preferences block, the starting address shown is the default value. You can change the starting value by entering the new value directly in Address when you select the memory segment to change.
From the starting address, Length sets the length of the memory allocated to the segment in Name. As in all memory entries, specify the length in hexadecimal format, in minimum addressable data units (MADUs). For the Analog Devices processor families, for example, the MADU is 8 bytes, 1 word.
Contents specifies the kind of program sections that you can store in the memory segment in Name. When you change the processor type, the kinds of information you can store in listed memory segments may change. Generally, the Contents list contains these strings:
Code — Allow code to be stored in the memory segment in Name.
Data — Allow data to be stored in the memory segment in Name.
Code and Data — Allow code and data to be stored in the memory segment in Name. When you add a new memory segment, this setting is the default for the contents of the new element.
You may add or use as many segments of each type as you need, within the limits of the memory on your processor.
Click Add to add a new memory segment to the processor memory map. When you click Add, a new segment name appears, for example NEWMEM1, in Name and on the list. In Name, change the temporary name NEWMEM1 by entering the new segment name. Entering the new name, or clicking OK updates the temporary name on the list to the name you enter.
Remove a memory segment from the memory map. Select the segment to remove from the list, and click Remove to delete the segment.
Enter the label for each option of the selected cache configuration, one label on each line, such as 0kb, 16kb, 32kb and so on.
Click Add to add a new cache configuration to the list. When you click Add, the new cache label appears on the list.
Remove a cache configuration from the cache list. Select the configuration to remove from the list, and click Remove to delete the cache.
Cache configurations and related options are defined as symbols to the project generator component. Cache options for new processors are not labeled until you add the labels.
Enter your label for the heap in the Label field. Entering the label updates the label of the selected configuration.
Options in this region let you specify where various program sections go in memory and the contents and label for each section. You can add text to describe each section. Program sections are distinct from memory segments—sections are portions of the executable code stored in contiguous memory locations. Commonly used sections include .text, .bss, .data, and .stack. Some sections relate to the compiler, and some can be custom sections as you require.
The name of the section corresponds to the symbolic name recognized by the linker program used with the respective processor.
Contents provides the information about the native of the program section. As the processor type for the target preferences block changes, the kinds of information you store in listed sections may change. Generally, the Contents list contains these strings:
Code — Allow code to be stored in the section in Name.
Data — Allow data to be stored in the section in Name.
Code and Data — Allow code and data to be stored in the section in Name. When you add a new section, this setting is the default for the contents.
You may add or use as many sections of each type as you need, within the limits of the memory on your processor.
Click Add to add a new section to the list. When you click Add, the new section appears on the list.
This option lets you remove a section from the section list. Select the section to remove from the list, and click Remove to delete the section.
Sections and related options are defined as symbols to the project generator component. Section options for new processors are not labeled until you add the labels.
The list on the left side of the pane shows the kinds of custom code you can specify for your processor. Each time you use your custom processor as defined in this dialog box, the custom code you enter in this field applies. You can enter custom code in the categories in the following table.
| Custom Code Entry | Description |
|---|---|
| Source files | Enter the full paths to source code files to use with this processor. By default there are no entries in this parameter. Enter each source file on a new line. |
| Include paths | If you require additional header files on your path, add them by typing the path into the text area, one file per line. The default setting does not include additional paths. |
| Libraries (Little Endian) | These entries identify specific little endian libraries that the processor requires. Add more as you require by entering the full path to the library with the library file in the text area. Enter one library per line. No additional libraries appear in the default configuration. |
| Libraries (Big Endian) | These entries identify specific big endian libraries that the processor requires. Add more as you require by entering the full path to the library with the library file in the text area. No additional libraries appear in the default configuration. Enter one library per line. |
| Preprocessor symbols | Enter any preprocessor symbols that the new processor requires for operation and compilation. No preprocessor symbols appear in the default configuration. Add the required symbols one symbol per line. |
You can use two types of tokens when you specify custom code paths:
$(Install_dir) — Refers to the installation directory of VisualDSP++ software. One example of this token is
$(Install_dir) \vdsplink\csl\lib\...
$(MATLAB_ROOT) — Refers to the directory where you installed your MATLAB software.
| Memory Copy | TigerSHARC Hardware Interrupt | |
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