Filter Design HDL Coder 2.3

Latest Features

Version 2.3

Released: 09 Oct 2008
 

Version 2.3, part of Release 2008b, includes the following enhancements:

• Automatic generation of HDL Cosimulation blocks, supporting verification of filter implementations in the Simulink environment with EDA simulator link products
• Expanded test bench generator with ability to partition test bench into code, data, and helper function files
• Other test bench enhancements, including support for specification of an initial value driven on test bench inputs and specification of data hold time for serial filters

See the Release Notes for details.

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Version 2.2

Released: 01 Mar 2008
 

Version 2.2, part of Release 2008a, includes the following enhancements:

• Code generation support for multirate Farrow sample rate converter filters (standalone or within a cascade)
• Support for multifile test-bench generation: option to generate separate files for test bench code, helper functions, and test bench data

See the Release Notes for details.

Version 2.1

Released: 01 Sep 2007
 

Version 2.1, part of Release 2007b, includes the following enhancements:

• Generation of M-file that captures code generation settings from GUI, allowing easy reconstruction of the filter and test-bench code
• Processor interface to support programmable coefficients for direct form FIR filters

See the Release Notes for details.

Version 2.0

Released: 01 Mar 2007
 

Version 2.0, part of Release 2007a, includes the following enhancements:

• HDL code generation support for Farrow filters and polyphase sample rate converters
• Enhanced speed and area trade-off options
• Enhanced GUI that supports the EDA Scripts dialog box and access to HDL code generation from the filterbuilder tool in Filter Design Toolbox

See the Release Notes for details.

Version 1.5

Released: 01 Sep 2006
 
Version 1.5, part of Release 2006b, includes the following enhancements:

• Distributed Arithmetic support for FIR Filters in HDL code generated for single-rate and multirate FIR filters
• Multirate support for generation of fully serial architectures for direct-form FIR polyphase decimators and interpolators
• Generate HDL dialog box support for full range of serial, parallel, and distributed arithmetic architecture options

See the Release Notes for details.