Simulink Verification and Validation 2.4

Product Description

• Introduction and Key Features
• Working with Simulink Verification and Validation
• Tracing Requirements to Designs, Tests, and Generated Code
• Assigning Verification Blocks to Test Signals
• Analyzing Model Coverage
• Enforcing Modeling Standards

Introduction

Simulink Verification and Validation exposes design flaws, inadequate requirements, incomplete tests, and unnecessary design constructs early in the development process. You can trace requirement documents to your design models, component tests, and generated code. You can also verify your designs and tests through model coverage and modeling standards checking.

Key Features

• Links requirements with Simulink and Stateflow objects, tests, and generated code
• Assigns verification blocks to test signals
• Identifies untested portions of your model using industry-standard coverage metrics, including MC/DC (modified condition/decision coverage)
• Checks Simulink and Stateflow models for compliance with modeling standards

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