Simulink Verification and Validation 2.4

Product Description

• Introduction and Key Features
• Working with Simulink Verification and Validation
• Tracing Requirements to Designs, Tests, and Generated Code
• Assigning Verification Blocks to Test Signals
• Analyzing Model Coverage
• Enforcing Modeling Standards

Assigning Verification Blocks to Test Signals

Assigning verification blocks to test signals defined in the Signal Builder block in Simulink lets you form component test cases and test harnesses that can be used to verify functional requirements during simulation. You can use a set of supplied assertion blocks directly or extend them to build more complex verification block libraries using the modeling capabilities in Simulink and Stateflow. Each component test can also be linked to requirements and used to evaluate the implementation of requirements in the model.

Component test cases can be combined to form a test harness and used to ensure that code corresponding to the model meets the same requirements that the model met during simulation. The test harness used for the model is applied against the generated code during software-in-the-loop (SIL) or processor-in-the-loop (PIL) testing.

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