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Simulink® Design Verifier™ 1.2

Generate tests and prove model properties using formal methods


Tests in a model harness and associated report generated by Simulink Design Verifier. These tests can then be run in simulation.

Simulink® Design Verifier™  software generates tests for your Simulink® and Stateflow® models that satisfy model coverage and user-defined objectives. It also proves model properties and generates examples of violations.

Learn more about Verification, Validation, and Test in Model-Based Design.


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Using MATLAB and Simulink for Verification and Validation in Government Organizations new