Simulink Design Verifier 1.3

Product Description

• Introduction and Key Features
• Working with Simulink Design Verifier
• Formal Methods with Prover® Plug-In
• Test Generation
• Property Proving
• Extending Design Verifier

Property Proving

Simulink Design Verifier proves the validity of functional requirements that you specify with blocks from the Simulink Model Verification and Simulink Design Verifier libraries. These blocks control the permissible values of signals in your model.

Simulink Design Verifier documents the valid blocks in a detailed report and generates counterexamples for invalid blocks. Counterexamples include input data and parameter values that demonstrate a specific violation. They are incorporated into the same style harness models that are produced during test generation. You can fine-tune counterexamples by using the Assumption block from the Simulink Design Verifier library.

Simulink Design Verifier supports both bounded and unbounded formal analysis techniques.

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