Free FPGA Design Information Kit

Learn how to streamline your FPGA design process with MATLAB and Simulink.

FPGA Design with Simulink Generate Verilog and VHDL Code with HDL Coder

MathWorks HDL code generation and verification products enable FPGA design engineers to quickly generate synthesizable Verilog and VHDL code for FPGA development. You can accelerate the design and verification of your FPGA projects by:

  • Generating readable and portable IEEE standards compliant HDL from MATLAB and Simulink
  • Creating target optimized HDL code for Xilinx and Altera FPGAs
  • Programming Xilinx and Altera FPGAs using integrated HDL synthesis workflow
  • Verifying your HDL code by cosimulating it with MATLAB and Simulink
  • Generating Verilog and VHDL test benches

Complete the form for access to technical resources that demonstrate how these products help produce high-performance FPGA designs in far less time than with conventional methods.


  • Introduction to HDL Coder
  • Introduction to Filter Design HDL Coder

Recorded Webinars

  • Rapid Design and Implementation Using Automatic HDL Code Generation
  • Advanced HDL Code Generation for FPGAs Using MATLAB and Simulink
  • Design and Verify Filter Designs for FPGAs
  • Image and Video Processing with DSPs and FPGAs
  • Using MATLAB and Simulink for FPGA Prototyping and Verification
  • Rapid FPGA Implementations with Model-Based Design
  • Rapid Design and Implementation of an FPGA-Based Digital Down Converter

User Stories

  • Semtech Speeds Development of Digital Receiver FPGAs and ASICs
  • Wolfson Microelectronics Accelerates Audio Hub Design Verification
  • Yokogawa Electric Develops Key Components for Next-Generation Optical Networks with Simulink and Mentor Graphics ModelSim
  • Faraday Accelerates SIP Development and Shrinks NAND Flash Controller ECC Engine Gate Count by 57% with Model-Based Design

Technical Literature

  • FPGA-Based Wireless System Design
  • Designing a Sigma-Delta ADC from Behavioral Model to Verilog and VHDL
  • Automatic Hardware Implementation of Digital Filters for an Audio Codec with MediaTek

Data Sheets

  • HDL Verifier
    Verify VHDL and Verilog using HDL simulators and FPGAs
  • Filter Design HDL Coder
    Generate HDL code for fixed-point filters
  • Fixed-Point Toolbox
    Design and execute fixed-point algorithms and analyze fixed-point data
  • Simulink Fixed Point
    Design and simulate fixed-point systems
  • HDL Coder
    Generate HDL code from Simulink models and MATLAB code