Learn how HDL code generation tools and techniques can significantly accelerate your FPGA design cycle. In this webinar, we will demonstrate use of Simulink HDL Coder to generate synthesizable HDL for an image processing application in five steps.
1. Build system model in Simulink
2. Analyze & optimize system design
3. Elaborate design for FPGA implementation
4. Generate HDL from Simulink model
5. Verify HDL
The demonstration also show how to link project requirements documents to the Simulink model, as well as to the generated HDL. A Q&A session will follow the presentation. This is the first of a three-part series on FPGA design using MATLAB and Simulink.
About the Presenter:
Stephan van Beek is a Signal Processing and Communications Engineer Application Engineer for MathWorks focused on FPGA implementation. Prior to joining MathWorks, Stephan worked at Anorad Europe BV as a field service engineer on motion control systems. After that he worked at Océ-Netherlands as an application engineer responsible for FPGA tool flows. Stephan studied electrical engineering at the Polytechnic in Eindhoven.
Recorded: 19 May 2010